A trend in modern integrated circuit manufacture is to produce semiconductor devices, such as field effect transistors (FETs), which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
Although the fabrication of smaller transistors allows more transistors to be placed on a single substrate for the formation relatively large circuit systems in a relatively small die area, this downscaling can result in the performance improvement but the degraded reliability. For example, the downscaling of n-channel field effect transistors (nFETs) and p-channel field effect transistors (pFETs) may result in a scaled inversion layer thickness (Tinv) being located between the gate metals and the semiconductor substrate to enhance the performance
In scaling of the devices, there remains a conflict to improve the reliability between nFET devices and pFET devices by adjusting dielectric thickness. For example, thinner dielectric material can improve the positive bias temperature instability (pBTI) reliability for nFET devices, whereas, thicker dielectric material can help the negative bias temperature instability (nBTI) reliability for pFET devices. However, it has been found to be difficult to make such adjustments using current technologies.